Interactive Creation of RTL Code from ESL IP for Low-Power Applications

PowerOpt is built on ChipVision's unique patented power analysis technology ORINOCO™.

PowerOpt is a true design tool (in contrast to the analysis tool ORINOCO) that enables chip designers to interactively work with the original input (ANSI-C or System-C) via a user guided inter-process scheduler. Designers trade off computation and communication resources across processes, along with a scheduling process with latency and pipelining detail. PowerOpt automatically implements various micro-architectures, optimizes them for energy consumption, area, and performance (latency), and compares them against each other, thus creating the optimal implementation.

PowerOpt generates RTL code automatically, bridging the gap from specification to implementation. In addition to the designer’s choice of the abstraction level of the generated RT model, from abstracted algorithm-level RTL or scheduled structural RTL, PowerOpt produces complementary dataflow and FSM bubble diagrams, and a test bench – one that matches the system-level source code from which it was derived.

PowerOpt is ideal for companies developing mobile communications, networking, consumer, or automotive applications, where extending battery life or reducing cooling requirements is important.

Pre-RTL energy savings:
PowerOpt enables trade-off analysis to create the lowest power implementations with up to 3x lower power consumption compared to the RTL flows.

Time to results:
PowerOpt operates on higher levels of abstraction, resulting in significantly faster time to results than lower-level methods.

Code Compactness:
Power optimization at the system level is much faster and enables multiple architectural explorations due to the code compactness compared to RTL code.